1. Field of the Invention
An object of the present invention is an improved integrated circuit for direct memory access to be interposed between a microprocessor and a communications cell. This invention can be used in the transfer of data between a memory and a peripheral.
2. Discussion of the Related Art
Direct memory access circuits are used to replace a microprocessor during data transfers between the memory of said microprocessor and a peripheral. This circuit can be used to free the microprocessor from the transferring task or to make up for any delay by the microprocessor during a transfer. The use of a direct memory access circuit is done commonly with mass memory type peripherals or communications port type peripherals. A direct memory access circuit receives instructions from a microprocessor. The instructions correspond to an indication of the start-of-transfer address, the direction of the transfer, the validation of the use of an interruption, the values of incrementation of the addresses, the suspension of operation, etc.
During a transfer of data with a peripheral, the microprocessor sends its instructions to the direct memory access circuit and then sends its instructions to the peripheral and the transfer takes place as follows:
the peripheral sends a signal requesting the transfer of one or more data elements to the direct memory access circuit; PA1 the direct memory access circuit informs the microprocessor that the direct memory access circuit controls the control bus, the address bus and the data bus of the system, PA1 the data element or elements are transferred between the peripheral and the memory under the control of the direct access memory, PA1 the control of the buses is released by the direct memory access circuit.
Since the peripherals are generally slower than the memory, the use of a direct memory access circuit prevents the microprocessor from having to save its internal registers in order to see to the transfer with the peripheral. This takes a certain amount of time and consequently spares the peripheral from having to wait for the transfer. All the transfer operations take place without any problem if the direction of transfer of the peripheral and of the direct memory access circuit are compatible. If the peripheral is a communications cell that interfaces information transfers with the exterior of the system, this amounts to saying that a reception of data, coming from the exterior of the system, corresponds, for the communications cell, to an operation of writing in the memory for the direct memory access circuit and that a transmission of data towards the exterior of the system corresponds, for the communications cell, to an operation of reading in the memory for the direct memory access circuit.
Should the peripheral be a communications cell, its role is to interpose itself between the buses of the microprocessor and a communications network. The communications cell takes responsibility, firstly, for the different impedance and power matching operations needed for the efficient operation of the communications network. Secondly, it will manage the data exchange protocol of the communications network. Now, in certain data transfer protocols, for example the so-called DDC protocol, the communications cell may act in the so-called "master" and "slave" modes. The "master" mode means that the communications cell will direct the communications network. The "slave" mode means that the communications cell will be directed by the communications network. During operation in "slave" mode, the communications cell will have to carry out data transfers whose direction is dictated by the communications network. If the memory access and the cell do not have compatible directions of transfer, a conflict will occur on the data bus: either no information is present or two information elements are present. While such conflicts are not destructive (the circuits are protected against brief short-circuits), the problem of the loss of information is quite real.
A first approach to this problem is a software approach. It consists in making the interface peripheral send an interruption message to the microprocessor so that the cell is managed by this microprocessor until the direction of transfer has been defined so as to transmit the direction of transfer to the direct memory access circuit. This kind of approach entails a substantial loss of time for the microprocessor and if it is busy with a task where a lot of time is needed before it can be released from this task, then a possible loss of data may occur if the information on direction of transfer is not transmitted with sufficient speed to the direct memory access circuit. Furthermore, the problem continues to be present, for the use of the direct memory access further slows down the microprocessor.
The invention is aimed at resolving the above-defined problem. According to the invention, links are added between a control register of the direct memory access circuit and the communications cell. By enabling an updating of the control register of the direct memory access circuit controlled by the communications cell, all the conflicts due to the direction of transfer are avoided and the microprocessor is unloaded.